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w25p10, w25p20 and w25p40 publication release date: november 28, 2005 - 1 - revision m 1m-bit, 2m-bit and 4m-bit serial flash memory with 40mhz spi formally nexflash nx25p10, nx25p20 and nx25p40 the winbond w25p10/20/40 are fully compatib le with the previous nexflash nx25p10/20/40 serial flash memories.
w25p10, w25p20 and w25p40 - 2 - table of contents- 1. general des cription ......................................................................................................... 4 2. features ....................................................................................................................... .......... 4 3. pin config urati on .............................................................................................................. .5 4. pin descri ption................................................................................................................ ..... 5 4.1 package ty pes ............................................................................................................... 5 4.2 chip select (/cs) ............................................................................................................ 5 4.3 serial data ou tput (do) ................................................................................................. 6 4.4 write protec t (/wp)......................................................................................................... 6 4.5 hold (/ho ld) ............................................................................................................... 6 4.6 serial clo ck (clk) .......................................................................................................... 6 4.7 serial data input (d i) ...................................................................................................... 6 5. block di agram .................................................................................................................. .... 7 6. functional des cription ................................................................................................... 8 6.1 spi operat ions ......................................................................................................... 8 6.1.1 spi m odes ...................................................................................................................... ..8 6.1.2 hold f uncti on .................................................................................................................. .8 6.2 write prot ection.................................................................................................... 8 6.2.1 write protect featur es......................................................................................................8 7. control and status registers..................................................................................... 9 7.1 status re gister ...................................................................................................... 9 7.1.1 busy........................................................................................................................... .....9 7.1.2 write enable lat ch (wel) ................................................................................................9 7.1.3 block protect bits (bp2, bp1, bp0)................................................................................10 7.1.4 reserved bits .................................................................................................................1 0 7.1.5 status register protect (s rp) ........................................................................................10 7.1.6 status register me mory prot ection ................................................................................11 7.2 instructio ns........................................................................................................... 11 7.2.1 manufacturer and device identific ation ...........................................................................12 7.2.2 instruction set (1) .............................................................................................................12 7.2.3 write disabl e (04h) .........................................................................................................13 7.2.4 write enabl e (06h) ..........................................................................................................13 7.2.5 read status regi ster ( 05h) ............................................................................................ 14 7.2.6 write status r egister (01h) ............................................................................................15 7.2.7 read data (03h) .............................................................................................................16 7.2.8 fast read (0bh) .............................................................................................................17 7.2.9 page program (02h) .......................................................................................................18 7.2.10 sector eras e (d8h) .......................................................................................................19
w25p10, w25p20 and w25p40 publication release date: november 28, 2005 - 3 - revision m 7.2.11 chip eras e (c7h) ..........................................................................................................20 7.2.12 power-down (b9h) ........................................................................................................21 7.2.13 release power-down / de vice id (abh) .......................................................................22 7.2.14 read manufacturer / de vice id (90h) ...........................................................................24 8. electrical chara cteristi cs......................................................................................... 25 8.1 absolute maximum ratings (1) .................................................................................... 25 8.2 operating ranges ......................................................................................................... 25 8.3 power-up timing and write inhibit thre shold .............................................................. 26 8.4 dc electrical characteristics (preliminary) (1) .............................................................. 27 8.5 ac measurement conditi ons........................................................................................ 28 8.6 ac electrical c haracterist ics ........................................................................................ 29 8.7 ac electrical charac teristics (c ont?d) ........................................................................... 30 8.8 serial output timi ng ..................................................................................................... 31 8.9 input ti ming .................................................................................................................. 3 1 8.10 hold ti ming................................................................................................................... 3 1 9. package specific ation .................................................................................................... 32 9.1 8-pin soic 150-mil (winbond package code sn) (nexflash package code n) ....... 32 10. ordering info rmation .................................................................................................... 33 11. revision history ............................................................................................................... .34
w25p10, w25p20 and w25p40 - 4 - 1. general description the w25p10 (1m-bit), w25p20 (2m-bit) and w25p40 (4m-bit) serial flash memories provide a storage solution for systems with limited space, pins and power. they are ideal for code download applications as well as storing voice, text and dat a. the devices operate on a single 2.7v to 3.6v power supply with current consumption as low as 4ma active and 1a for power-down. all devices are offered in space-saving 8-pin soic type packages as shown below. contact winbond for availability of alternate packages. as part of a family of serial flash products, winbond also provides a compatible migration path to 8m/16m/32m-bit densities. the w25p10/20/40 array is organized into 512/ 1024/2048 programmable pages of 256-bytes each. a single byte or, up to 256 bytes, can be programmed at a time using the page program instruction. pages are grouped into 2/4/8 erasable sectors of 256 pages (64k-byte) each as shown in figure 2. both sector erase and chip (full chip ) erase instructions are supported. the serial peripheral interface (spi) consists of four pins (serial clock, chip select, serial data in and serial data out) that support high speed serial data transfers up to 40mhz. a hold pin, write protect pin and programmable write pr otect features provide further c ontrol flexibility. additionally, the device can be queried for manufacturer and device id. s pecial customer id (for copy authentication) and factory programming is available, contact winbond for more information. the winbond w25p10/20/40 are fully compatible with the previous nexflash nx25p10/20/40 serial flash memories. 2. features ? 1m / 2m / 4m-bit serial flash memories ? family of serial flash memories ? w25p10: 1m-bit/128k-byte (131,072) ? w25p20: 2m-bit/256k-byte (262,144) ? w25p40: 4m-bit/512k-byte (524,288) ? 256-bytes per programmable page ? migration path to 8m/16m/32m-bit ? 4-pin spi serial interface ? clock, chip select, data in, data out ? easily interfaces to popular microcontrollers ? compatible with spi modes 0 and 3 ? bottom boot organization (standard) ? optional hold function for spi flexibility ? low power consumption, wide temperature range ? single 2.7 to 3.6v supply ? 4ma active current, 1a power-down (typ) ? -40 to +85c operating range ? fast and flexible serial data access ? 40mhz fast read, 33mhz standard read ? byte-addressable read and program ? auto-increment read capability ? manufacturer and device id ? programming features ? page program up to 256 bytes <2ms ? sector erase (64k-byte) 2 seconds ? chip erase: 3 seconds (25p10/20), 5 seconds (25p40) ? 100,000 erase/write cycles ? twenty-year data retention ? software and hardware write protection ? write-protect all or portion of memory ? enable/disable protection with /wp pin ? space saving package ? tiny 8-pin soic 150mil ? ideal for systems with limited pins, space, and power ? controller-based serial code-download ? c systems storing data, text or voice ? battery-operated and portable products
w25p10, w25p20 and w25p40 publication release date: november 28, 2005 - 5 - revision m 3. pin configuration figure 1. w25p10, w25p20 and w25p40 pi n assignments, 8-pin soic 150-mil 4. pin description pin no. pin name i/o function 1 /cs i chip select input 2 do o data output 3 /wp i write protect input 4 gnd ground 5 di i data input 6 clk i serial clock input 7 /hold i hold input 8 vcc power supply 4.1 package types the standard package for the w25p10/20/40 is an 8-pin plastic soic with 150-mil body (winbond package code sn) (nexflash package code n). it also allows a package migration path to higher density serial flash devices. the pinout for the package is shown in figure 1. package diagrams and dimensions are illustrated at the end of this data sheet. optional 8-contact mlp packages may be available. please contact winbond for further mlp package information. 4.2 chip select (/cs) the spi chip select (/cs pin enables and disables device operation. when /cs is high the device is deselected and the serial data output (do) pin is at high impedance. when deselected, the devices power consumption will be at standby levels unless an in ternal erase, program or status register cycle is in progress. when /cs is brought low the devic e will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. after power-up, /cs must transition from high to low before a new inst ruction will be accepted. the /cs input must track
w25p10, w25p20 and w25p40 - 6 - the vcc supply level at power-up (see ?write pr otection? and figure 16). if needed a pull-up resister on /cs can be used to accomplish this. 4.3 serial data output (do) the spi serial data output (do) pin provides a means for data and status to be serially read from (shifted out of) the device. data is shifted out on the falling edge of the serial clock (clk) input pin. 4.4 write protect (/wp) the write protect (/wp) pin can be used to prevent the status register from being written. used in conjunction with the status register?s block pr otect (bp2, bp1, and bp0) bits and status register protect (srp) bits, a portion or the entire memory array can be hardware protected. the /wp pin is active low. 4.5 hold (/hold) the /hold pin allows the device to be paused while it is actively selected. when /hold is brought low, while /cs is low, the do pin will be at high impedance and signals on the di and clk pins will be ignored (don?t care). when /hold is brought high, device operation can resume. the /hold function can be useful when multiple devices are shari ng the same spi signals. (?see hold function?) 4.6 serial clock (clk) the spi serial clock input (clk) pin provides t he timing for serial input and output operations. ("see spi "operations") 4.7 serial data input (di) the spi serial data input (di) pin provides a m eans for instructions, addresses and data to be serially written to (shifted into) the device. data is latc hed on the rising edge of the se rial clock (clk) input pin.
w25p10, w25p20 and w25p40 publication release date: november 28, 2005 - 7 - revision m 5. block diagram figure 2. w25p10, w25p20 and w25p40 block diagram
w25p10, w25p20 and w25p40 - 8 - 6. functional description 6.1 spi operations 6.1.1 spi modes the w25p10/20/40 is accessed through an spi compatible bus consisting of four signals: serial clock (clk), chip select (/cs), serial data input (di) and serial data output (do). both spi bus operation modes 0 (0,0) and 3 (1,1) are supported. the primary difference between mode 0 and mode 3 concerns the normal state of the clk signal when the spi bus master is in standby and data is not being transferred to the serial flash. for mode 0 t he clk signal is normally low. for mode 3 the clk signal is normally high. in either case data input on the di pin is sampled on the rising edge of the clk. data output on the do pin is clocked out on the falling edge of clk. 6.1.2 hold function the /hold signal allows the w25p10/20/40 operation to be paused while it is actively selected (when /cs is low). the /hold function may be useful in cases w here the spi data and clock signals are shared with other devices. for example, consider if the page buffer was only partially written when a priority interrupt requires use of the spi bus. in this case the /hold function can save the state of the instruction and the data in the buffer so programmi ng can resume where it left off once the bus is available again. to initiate a /hold condition, the device must be selected with /cs low. a /hold condition will activate on the falling edge of the /hold signal if the clk signal is already low. if the clk is not already low the /hold condition will activate after the next falling edge of clk. the /hold condition will terminate on the rising edge of the /hold signal if the clk signal is already low. if the clk is not already low the /hold condition will terminate after the next falling edge of clk. during a /hold condition, the serial data output (do) is high impedance, and serial data input (di) and serial clock (clk) are ignored. the chip select (/cs) signal should be kept active (low) for the full duration of the /hold operation to avoid resetting the inte rnal logic state of the device. 6.2 write protection applications that use non-volatile memory must ta ke into consideration the possibility of noise and other adverse system conditions that may compromi se data integrity. to address this concern the w25p10/20/40 provides several means to protect data from inadvertent writes. 6.2.1 write protect features ? device resets when vcc is below threshold. ? time delay write disable after power-up. ? write enable/disable instructions. ? automatic write disable after program and erase. ? software write protection using status register. ? hardware write protection using status register and /wp pin. ? write protection using power-down instruction.
w25p10, w25p20 and w25p40 publication release date: november 28, 2005 - 9 - revision m upon power-up or at power-down the w25p10/20/40 will maintain a reset condition while vcc is below the threshold value of v wi , (see power-up timing and voltage levels and figure 17). while reset, all operations are disabled and no instructi ons are recognized. during power-up and after the vcc voltage exceeds v wi , all program and erase related instructions are further disabled for a time delay of t puw . this includes the write enable, page program , sector erase, chip erase and the write status register instructions. note that the chip select pin (/cs) must track the vcc supply level at power-up until the vcc-min level and t vsl time delay is reached. if needed a pull-up resister on /cs can be used to accomplish this. after power-up the device in automatically placed in a write-disabled state with the status register write enable latch (wel) set to a 0. a write enable instruction must be issued before a page program, sector erase, chip erase or write stat us register instruction will be accepted. after completing a program, erase or write instruction the write enable latch (we l) is automatically cleared to a write-disabled state of 0. software controlled write protection is facilitated using the write stat us register instruction and setting the status register protect (srp ) and block protect (bp2, bp1, and bp0 ) bits. these status register bits allow a portion or all of the memory to be c onfigured as read only. used in conjunction with the write protect (/wp) pin, changes to the status register can be enabled or disabled under hardware control. see status register for further information. additionally, the power-down instruction offers an extra level of write protection as all instructions are ignored except for the releas e power-down instruction. 7. control and status registers the read status register instruction can be used to provide status on the av ailability of the flash memory array, if the device is write enabled or dis abled, and the state of writ e protection. the write status register instruction can be used to configure the devices wr ite protection features. see figure 3. 7.1 status register 7.1.1 busy busy is a read only bit in the status register (s0) t hat is set to a 1 state w hen the device is executing a page program, sector erase, chip erase or write st atus register instructi on. during this time the device will ignore further instructions except fo r the read status regist er instruction (see t w , t pp , t se and t ce in ac characteristics). when the program, eras e or write status regi ster instruction has completed, the busy bit will be cleared to a 0 st ate indicating the device is ready for further instructions. 7.1.2 write enable latch (wel) write enable latch (wel) is a read only bit in the status register (s1) that is set to a 1 after executing a write enable instruction. the we l status bit is cleared to a 0 w hen the device is write disabled. a
w25p10, w25p20 and w25p40 - 10 - write disable state occurs upon power-up or after any of the following instructi ons: write disable, page program, sector erase, chip er ase and write status register. 7.1.3 block protect bits (bp2, bp1, bp0) the block protect bits (bp2, bp1, bp0 ) are non-volatile read/write bits in the status register (s4, s3, s2) that provide write protection control and status. block protect bits can be set using the write status register instruction (see tw in ac characte ristics). all, none or a portion of the memory array can be protected from program and erase instructions (see status register memory protection table). the factory default setting for the block protection bi ts is 0, none of the array protected. the block protect bits can not be written to if the status r egister protect (srp) bit is set to 1 and the write protect (/wp) pin is low. the w25p20 and w25p10 do not use bp2. 7.1.4 reserved bits status register bit locations 5 and 6 are reserved fo r future use. current devices will read 0 for these bit locations. it is recommended to mask out the rese rved bit when testing the status register. doing this will ensure compatibilit y with future devices. 7.1.5 status register protect (srp) the status register protect (srp) bi t is a non-volatile read/write bit in the status register (s7) that can be used in conjunction with the write protect (/wp) pi n to disable writes to the status register. when the srp bit is set to a 0 state (factory default) t he /wp pin has no control over the status register. when the srp pin is set to a 1, the write status regi ster instruction is locked out while the /wp pin is low. when the /wp pin is high the write st atus register instruction is allowed. figure 3. status register bit locations
w25p10, w25p20 and w25p40 publication release date: november 28, 2005 - 11 - revision m 7.1.6 status register memory protection status register (1) w25p40 (4m-bit) memory protection bp2 bp1 bp0 sector(s) addresses density (kb) portion 0 0 0 none none none none 0 0 1 7 070000h - 07ffffh 512k-bit upper 1/8 0 1 0 6 and 7 060000h - 07ffffh 1m-bit upper 1/4 0 1 1 4 thru 7 040000h - 07ffffh 2m-bit upper 1/2 1 x x all 000000h - 07ffffh 4m-bit all status register (1) w25p20 (2m-bit) memory protection bp2 bp1 bp0 sector(s) addresses density (kb) portion x 0 0 none none none none x 0 1 3 030000h - 03ffffh 512k-bit upper 1/4 x 1 0 2 and 3 020000h - 03ffffh 1m-bit upper 1/2 x 1 1 all 000000h - 03ffffh 2m-bit all status register (1) w25p10 (1m-bit) memory protection bp2 bp1 bp0 sector(s) addresses density (kb) portion x 0 x none none none none x 1 0 none none none none x 1 1 all 000000h - 01ffffh 1m-bit all note: 1. x = don?t care 7.2 instructions the instruction set of the w25p10/20/ 40 consists of twelve basic instru ctions that are fully controlled through the spi bus (see instruction set table). instru ctions are initiated with the falling edge of chip select (/cs). the first byte of data clocked into t he di input provides the in struction code. data on the di input is sampled on the rising edge of clo ck with most significant bit (msb) first. instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don?t care), and in some ca ses, a combination. inst ructions are completed with the rising edge of edge /cs. clock relative ti ming diagrams for each instruction are included in figures 4 through 16. all read instructions can be completed after any clocked bit. however, all instructions that write, program or erase must complete on a byte boundary (/cs driven high after a full 8-bits have been clocked) otherwise the instructi on will be terminated. this feature further protects the device from inadvertent writes . additionally, while the memory is being programmed or erased, or when the status register is being written, all inst ructions except for read status register will be ignored until the program or erase cycle has completed.
w25p10, w25p20 and w25p40 - 12 - 7.2.1 manufacturer and device identification manufacturer id (m7-m0) winbond serial flash efh device id (id7-id0) w25p10 10h w25p20 11h w25p40 12h 7.2.2 instruction set (1) instruction name byte 1 code byte 2 (5) byte 3 byte 4 byte 5 byte 6 n-bytes write enable 06h write disable 04h read status register 05h (s7?s0) (1) (2) write status register 01h s7?s0 read data 03h a23?a16 a15?a8 a7?a0 (d7?d0) (next byte) continuous fast read 0bh a23?a16 a15?a8 a7?a0 dummy (d7?d0) (next byte) continuous page program 02h a23?a16 a15?a8 a7?a0 (d7?d0) (next byte) up to 256 bytes sector erase d8h a23?a16 a15?a8 a7?a0 (6) chip erase c7h power-down b9h release power- down / device id abh dummy dummy dummy (id7-id0) (3) manufacturer/ device id 90h dummy dummy 00h (m7-m0) (id7-id0) (4) notes: 1. data bytes are shifted with most si gnificant bit first. byte fields with data in parenthesis ?( )? indicate data being read from the device on the do pin. 2. the status register content s will repeat continuously until /cs terminates the instruction. 3. the device id will repeat continuously until /cs terminates the instruction. 4. the manufacturer id and device id bytes will repeat continuously until /cs termi nates the instruction. 5. unused upper address bits must be set to a 0 for the w25p10. 6. the lowest 16 address bits (a15-a0) must be set to 0.
w25p10, w25p20 and w25p40 publication release date: november 28, 2005 - 13 - revision m 7.2.3 write disable (04h) the write enable instruction (figure 4) sets the write enable latch (wel) bit in the status register to a 1. the wel bit must be set prior to every page pr ogram, sector erase, chip erase and write status register instruction. the write e nable instruction is entered by drivi ng /cs low, shifting the instruction code ?06h? into the data input (di) pin on t he rising edge of clk, and then driving /cs high. figure 4. write disable in struction sequence diagram 7.2.4 write enable (06h) the write disable instruction (figure 5) resets the write enable latch (wel) bit in the status register to a 0. the write disable instruction is entered by driving /cs low, shifting the instruction code ?04h? into the di pin and then driving /cs high. note that the wel bit is automatically reset after power-up and upon completion of the write status register , page program, sector erase, and chip erase instructions. figure 5. write enable instruction sequence diagram
w25p10, w25p20 and w25p40 - 14 - 7.2.5 read status register (05h) the read status register instructi on allows the 8-bit status register to be read. the instruction is entered by driving /cs low and shifting the instructi on code ?05h? into the di pin on the rising edge of clk. the status register bits ar e then shifted out on the do pin at the falling edge of clk with most significant bit (msb) first as shown in figure 6. the status register bits are shown in figure 3 and include the busy, wel, bp2-bp0, and srp bits (see descr iption of the status register earlier in this data sheet). the status register instruction may be used at any time, even while a program, erase or write status register cycle is in progress. this allows the busy status bit to be checked to determine when the cycle is complete and if the device can accept anot her instruction. the stat us register can be read continuously, as shown in figure 6. the inst ruction is completed by driving /cs high. figure 6. read status register instruction sequence diagram
w25p10, w25p20 and w25p40 publication release date: november 28, 2005 - 15 - revision m 7.2.6 write status register (01h) the write status register instruction allows t he status register to be written. a write enable instruction must previously have been executed for the device to acc ept the write status register instruction (status register bit wel must equal 1) . once write enabled, the in struction is entered by driving /cs low, sending the instruction code ?01h?, and then writing the status register data byte as illustrated in figure 7. the status register bits are shown in figure 3 and described earlier in this data sheet. only non-volatile status register bits srp, bp2, bp1 and bp0 (bits 7, 4, 3 and 2) can be written to. all other status register bit locations are r ead-only and will not be affected by the write status register instruction. the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the write status register inst ruction will not be executed. after /cs is driven high, the self-timed write status register cycle will commence for a time duration of t w (see ac characteristics). while the write status register cycle is in progress, the read status regi ster instruction may still accessed to check the status of the busy bit. the busy bit is a 1 during the write status register cycle and a 0 when the cycle is finished and ready to accept ot her instructions again. a fter the write register cycle has finished the write enable latch (wel) bit in the status register will be cleared to 0. the write status register instru ction allows the block protect bits (bp2, bp1 and bp0) to be set for protecting all, a portion, or none of the memory fr om erase and program instructions. protected areas become read-only (see status register memory pr otection table). the write status register instruction also allows the status register protect bit (srp) to be set. this bit is used in conjunction with the write protect (/wp) pin to disable writes to the status register. when the srp bit is set to a 0 state (factory default) the /wp pin has no control over the status regi ster. when the srp pin is set to a 1, the write status register inst ruction is locked out while the /wp pin is low. when the /wp pin is high the write status register instruction is allowed. figure 7. write status register instruction sequence diagram
w25p10, w25p20 and w25p40 - 16 - 7.2.7 read data (03h) the read data instruction allows one or more dat a bytes to be sequentially read from the memory. the instruction is initiated by driving the /cs pin low and then shifting the instruction code ?03h? followed by a 24-bit address (a23-a0) into the di pin. the code and address bits are latched on the rising edge of the clk pin. after the address is re ceived, the data byte of the addressed memory location will be shifted out on the do pin at the falli ng edge of clk with most significant bit (msb) first. the address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. this means that the entire memory can be accessed with a single instruction as long as the clock continues. the instruction is completed by driving /cs high. the read data instruction sequence is shown in figur e 8. if a read data instruction is issued while an erase, program or write cycle is in process (bu sy=1) the instruction is ignored and will not have any effects on the current cycle. the r ead data instruction allows clock rates from d.c. to a maximum of f r (see ac electrical characteristics). figure 8. read data instruction sequence diagram
w25p10, w25p20 and w25p40 publication release date: november 28, 2005 - 17 - revision m 7.2.8 fast read (0bh) the fast read instruction is similar to the read da ta instruction except t hat it can operate at the highest possible frequency of f r (see ac electrical characteristi cs). this is accomplished by adding a ?dummy? byte after the 24-bit address as shown in figure 9. the dummy byte allows the devices internal circuits additional time for setting up the in itial address. the dummy byte data value on the di pin is a ?don?t care?. figure 9. fast read instruction sequence diagram
w25p10, w25p20 and w25p40 - 18 - 7.2.9 page program (02h) the page program instruction allows from one byte to 256 bytes of data to be programmed at memory locations previously erased to all 1s (ffh). a write enable instruction mu st be executed before the device will accept the page program instruction (status register bit wel must equal 1). the instruction is initiated by drivi ng the /cs pin low then shifting the in struction code ?02h? followed by a 24-bit address (a23-a0) and at least one data byte, into the di pin. the /cs pin must be driven low for the entire length of the instruction while data is being sent to the dev ice. the page program instruction sequence is shown in figure 10. if an entire 256 byte page is to be programmed, the la st address byte (the 8 least significant address bits) should be set to 0. if the last address byte is not zero, and the number of clocks exceed the remaining page length, the addressing will wrap to the beginning of the page. less than 256 bytes can be programmed without having any e ffect on other bytes within the same page. if more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. as with the write and erase instructions, the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the page pr ogram instruction will not be executed. after /cs is driven high, the self-timed page program instruction will commence for a time duration of tpp (see ac characteristics). while the page program cycl e is in progress, the read status register instruction may still be accessed for checking the st atus of the busy bit. the busy bit is a 1 during the page program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after t he page program cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the p age program instruction w ill not be executed if the addressed page is protected by the block protect ( bp2, bp1, bp0) bits (see status register memory protection table). figure 10. page program instruction sequence diagram
w25p10, w25p20 and w25p40 publication release date: november 28, 2005 - 19 - revision m 7.2.10 sector erase (d8h) the sector erase instruction sets all memory within a specified sector to the erased state of all 1s (ffh). a write enable instruction must be execut ed before the device will accept the erase sector instruction (status register bit wel must equal 1). t he instruction is initiated by driving the /cs pin low and shifting the instruction code ?d8h? follow ed a 24-bit sector address (a23-a0) (see figure 2). the lowest 16 address bits (a15-a0) must be set to 0. the sector erase instruction sequence is shown in figure 11. the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the sector erase instruction w ill not be executed. after /cs is dr iven high, the self-timed sector erase instruction will commence for a time duration of t se (see ac characteristics). while the sector erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 duri ng the sector erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the sector erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the sector erase instruction will not be exec uted if the addressed page is protec ted by the block protect (bp2, bp1, bp0) bits (see status regist er memory protection table). figure 11. sector erase instruction sequence diagram
w25p10, w25p20 and w25p40 - 20 - 7.2.11 chip erase (c7h) the chip erase instruction sets all memory within the device to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will acc ept the chip erase instruction (status register bit wel must equal 1). the instru ction is initiated by driving the /cs pin low and shifting the instruction code ?c7h?. the chip er ase instruction sequence is shown in figure 12. the /cs pin must be driven high after the eighth bit has been latched. if this is not done the chip erase instruction will not be executed. after /cs is driven high, the self-timed chip erase instruction will commence for a time duration of t ce (see ac characteristics). while the chip erase cycle is in progress, the read status register instruction may still be accessed to check the status of the busy bit. the busy bit is a 1 during the chip erase cy cle and becomes a 0 when finished and the device is ready to accept other instructi ons again. after the chip erase cy cle has finished the write enable latch (wel) bit in the status register is cleared to 0. the chip erase instruction will not be executed if any page is protected by the block protect (bp2, bp1, bp0) bits (see status register memory protection table). figure 12. chip erase instruction sequence diagram
w25p10, w25p20 and w25p40 publication release date: november 28, 2005 - 21 - revision m 7.2.12 power-down (b9h) although the standby current during nor mal operation is relatively low, standby current can be further reduced with the power-down instruction. the lower power consumption makes the power-down instruction especially useful for battery pow ered applications (see icc1 and icc2 in ac characteristics). the instruction is initiated by driving the /cs pin low and shifting the instruction code ?b9h? as shown in figure 13. the /cs pin must be driven high after the eighth bit has been latched. if this is not done the power- down instruction will not be executed. after /cs is driven high, the power-down state will entered within the time duration of t dp (see ac characteristics). while in the power-down state only the release from power-down / device id instruction, which restores the device to normal operation, will be recognized. all other instructions are ignored. this includes the r ead status register instruction, which is always available during normal operation. ignoring all but one instruction makes the power down state a useful condition for securing maximum write protection. the device always powers-up in the normal operation with t he standby current of icc1. figure 13. deep power-down instruction sequence diagram
w25p10, w25p20 and w25p40 - 22 - 7.2.13 release power-down / device id (abh) the release from power-down / device id instructi on is a multi-purpose instruction. it can be used to release the device from the power- down state, obtain the devices elec tronic identification (id) number or do both. when used only to release the device from the power- down state, the instructi on is issued by driving the /cs pin low, shifting the instruction code ?abh ? and driving /cs high as shown in figure 14. after the time duration of t res1 (see ac characteristics) the devic e will resume normal operation and other instructions will be accepted. the /cs pin must remain high during the t res1 time duration. when used only to obtain the device id while not in the power-down state, the instruction is initiated by driving the /cs pin low and shifting the instru ction code ?abh? followed by 3-dummy bytes. the device id bits are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 15. the device id values for the w25p10, w25p20, and w 25p40 are listed in the manufacturer and device identificati on table. the device id can be read continuously. the instruction is completed by driving /cs high. when used to release the device from the power-dow n state and obtain the devi ce id, the instruction is the same as previously described, and shown in figure 13, except that after /cs is driven high it must remain high for a time duration of t res2 (see ac characteristics). after this time duration the device will resume normal operation and ot her instructions will be accepted. if the release from power-down / device id instru ction is issued while an erase, program or write cycle is in process (when busy equals 1) the inst ruction is ignored and will not have any effects on the current cycle. figure 14. release power-down instruction sequence
w25p10, w25p20 and w25p40 publication release date: november 28, 2005 - 23 - revision m figure 15. release power-down / devi ce id instruction sequence diagram
w25p10, w25p20 and w25p40 - 24 - 7.2.14 read manufacturer / device id (90h) the read manufacturer/device id instruction is an alternative to the release from power-down / device id instruction that prov ides both the jedec assigned manufac turer id and the specific device id. the read manufacturer/device id instruction is very similar to the release from power-down / device id instruction. the instruction is initiated by driving the /cs pin low and shifting the instruction code ?90h? followed by a 24-bit address (a23-a0) of 000000h. after which, the manufacturer id for winbond (efh) and the device id are shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 16. the device id values fo r the w25p10, w25p20, and w 25p40 are listed in the manufacturer and device identificati on table. if the 24-bit address is initially set to 000001h the device id will be read first and then followed by the manuf acturer id. the manufacturer and device ids can be read continuously, alternating from one to the other . the instruction is completed by driving /cs high. figure 16. read manufacturer / device id diagram
w25p10, w25p20 and w25p40 publication release date: november 28, 2005 - 25 - revision m 8. electrical characteristics 8.1 absolute maximum ratings (1) parameters symbol conditions range unit supply voltage vcc ?0.6 to +4.0 v voltage applied to any pin v io relative to ground ?0.6 to vcc +0.4 v storage temperature t stg ?65 to +150 c lead temperature t lead see note 2 c electrostatic discharge voltage v esd human body model (3) ?2000 to +2000 v notes: 1 this device has been designed and tested for the specified operation ranges. proper operat ion outside of these levels is not guaranteed. exposure beyond absolute maximum ratings (listed above) may cause permanent damage. 2. compliant with jedec standard j-std-20c for small body sn -pb or pb-free (green) assembly and the european directive on restrictions on hazardous s ubstances (rohs) 2002/95/eu.. 3. jedec std jesd22-a114a (c1=100 pf, r1=1500 ohms, r2=500 ohms). 8.2 operating ranges spec parameter symbol conditions min max unit supply voltage (1) vcc f r = 33mhz, f r = 25mhz f r = 40mhz, f r = 25mhz 2.7 3.0 3.6 3.6 v v ambient temperature, operating t a industrial ?40 +85 c note: 1. vcc voltage during read can operate across the min and ma x range but should not exceed 10% of the programming (erase/write) voltage.
w25p10, w25p20 and w25p40 - 26 - 8.3 power-up timing and write inhibit threshold spec parameter symbol min max unit vcc (min) to /cs low t vsl (1) 10 s time delay before write instruction t puw (1) 1 10 ms write inhibit threshold voltage v wi (1) 1 2 v note: 1. these parameters are characterized only. figure 17. power-up timing and voltage levels
w25p10, w25p20 and w25p40 publication release date: november 28, 2005 - 27 - revision m 8.4 dc electrical characteristics (preliminary) (1) spec parameter symbol conditions min typ max unit input capacitance c in (2) v in = 0v (2) 6 pf output capacitance cout (2) v out = 0v (2) 8 pf input leakage i li 2 a i/o leakage i lo 2 a standby current i cc 1 /cs = vcc, vin = gnd or vcc 25 50 a power-down current i cc 2 /cs = vcc, vin = gnd or vcc <1 5 a current read data 1mhz i cc 3 c = 0.1 vcc / 0.9 vcc do = open 4 7 ma current read data 20mhz c = 0.1 vcc / 0.9 vcc do = open 10 14 ma current read data 33mhz c = 0.1 vcc / 0.9 vcc do = open 14 18 ma current page program i cc 4 /cs = vcc 15 20 ma current write status register i cc 5 /cs = vcc 8 20 ma current sector erase i cc 6 /cs = vcc 15 25 ma current chip erase i cc 7 /cs = vcc 17 25 ma input low voltage v il ?0.5 vcc x0.3 v input high voltage v ih vcc x0.7 vcc +0.4 v output low voltage v ol i ol = 1.6 ma 0.4 v output high voltage v oh i oh = ?100 a vcc ?0.2 v notes: 1. see preliminary designation. 2. tested on sample basis and specified through desi gn and characterization data. ta=25 c, vcc 3v.
w25p10, w25p20 and w25p40 - 28 - 8.5 ac measurement conditions spec parameter symbol min max unit load capacitance c l 30 30 pf input rise and fall times t r , t f 5 ns input pulse voltages v in 0.2 vcc to 0.8 vcc v output timing reference voltages o ut 0.3 vcc to 0.7 vcc v note: 1. output hi-z is defined as the poi nt where data out is no longer driven. figure 18. ac measurement i/o waveform
w25p10, w25p20 and w25p40 publication release date: november 28, 2005 - 29 - revision m 8.6 ac electrical characteristics spec description symbol alt min typ max unit clock frequency, for fast read (0bh) and all other instructions except read data (03h) 2.7v-3.6v vcc (25p10 & 25p20 / 25p40) 3.0v-3.6v vcc f r f c d.c. d.c. 25/33 40 mhz mhz clock freq. read data instruction (03h) f r d.c. 25 mhz clock high, low time, for fast read (0bh) and all other instructions except read data (03h) t clh , t cll (1) 11 ns clock high, low time for read data instruction t crlh , t crll (1) 11 ns clock rise time peak to peak t clch (2) 0.1 v/ns clock fall time peak to peak t chcl (2) 0.1 v/ns /cs active setup time relative to clk t slch t css 5 ns /cs not active hold time relative to clk t chsl 5 ns data in setup time t dvch t dsu 2 ns data in hold time t chdx t dh 5 ns /cs active hold time relative to clk (2.7v-3.6v / 3.0v-3.6v) t chsh 7/5 ns /cs not active setup time relative to clk t shch 5 ns /cs deselect time t shsl t csh 100 ns output disable time t shqz (2) t dis 9 ns clock low to output valid (2.7v-3.6v / 3.0v-3.6v) t clqv t v 13/9 ns output hold time t clqx t ho 0 ns /hold active setup time relative to clk (2.7v-3.6v / 3.0v-3.6v) t hlch 6/5 ns continued ? next page
w25p10, w25p20 and w25p40 - 30 - 8.7 ac electrical characteristics ( cont?d) spec description symbol alt min typ max unit /hold active hold time relative to clk t chhh 5 ns /hold not active setup time relative to clk t hhch 5 ns /hold not active hold time relative to clk t chhl 5 ns /hold to output low-z t hhqx (2) t lz 9 ns /hold to output high-z t hlqz (2) t hz 9 ns write protect setup time before /cs low t whsl (4) 20 ns write protect hold time after /cs high t shwl (4) 100 ns /cs high to power-down mode t dp (2) 3 s /cs high to standby mode without electronic signature read t res 1 (2) 3 s /cs high to standby mode with electronic signature read t res 2 (2) 1.8 s write status register cycle time t w 10 15 ms page program cycle time t pp 2 5 ms sector erase cycle time t se 0.7 3 s chip erase cycle time w25p10 and w25p20 chip erase cycle time w25p40 t ce 3 5 6 10 s s notes: 1. clock high + clock low must be less than or equal to 1/f c . 2. value guaranteed by design and/or charac terization, not 100% tested in production. 3. expressed as a slew-rate. 4. only applicable as a constraint for a write status register instruction w hen sector protect bit is set at 1.
w25p10, w25p20 and w25p40 publication release date: november 28, 2005 - 31 - revision m 8.8 serial output timing 8.9 input timing 8.10 hold timing
w25p10, w25p20 and w25p40 - 32 - 9. package specification 9.1 8-pin soic 150-mil (winbond package code sn) millimeters inches symbol min typ. max min typ. max a 1.47 1.60 1.72 0.058 0.063 0.068 a1 0.10 --- 0.24 0.004 --- 0.009 a2 --- 1.45 --- --- 0.057 --- b 0.33 0.41 0.50 0.013 0.016 0.020 c 0.19 0.20 0.25 0.0075 0.008 0.0098 d (3) 4.80 4.85 4.95 0.189 0.191 0.195 e 5.80 6.00 6.19 0.228 0.236 0.244 e1 (3) 3.80 3.90 4.00 0.150 0.154 0.157 e (2) 1.27 bsc 0.050 bsc l 0.40 0.71 1.27 0.015 0.028 0.050 0 o --- 8 o 0 o --- 8 o cp --- --- 0.10 --- --- 0.004 notes: 1. controlling dimensions: inches , unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusi ons and should be measured from the bottom of the package. 4. formed leads shall be planar with respect to one another within .0004 inches at the seating plane.
w25p10, w25p20 and w25p40 publication release date: november 28, 2005 - 33 - revision m 10. ordering information
w25p10, w25p20 and w25p40 - 34 - 11. revision history version date page description a 04/29/03 new create b 09/12/03 incorporated spiflash trademark for w25p10, 20 and 40 product family. adjusted data for consistency c 03/09/04 10, 11, 14, 16, 24 adjusted pages for technical clarity. updated special options and ordering information d 03/24/04 mlp metal die pad notification; under "package types," figure 3 and packaging information. e 05/11/04 corrected dimensions in packaging information section for 6x5mm mlp. updated characterization information dc & ac f 06/16/04 modified dimensional data in the packaging information for the 6x5mm mlp package g 11/23/04 added fr = 40mhz @ 3.0v to 3.6v vcc. added fr = 33mhz @ 3.0v to 3.6v vcc. modified t lead in absolute maximum ratings to reference jedec standard information. added f r and f r conditions to operating ranges. updated i cc 3 and i cc 5 data in dc electrical characteristics. added 20/33mhz call outs and updated min, max and typ data in ac electrical characteristics h 12/08/04 updated 8-pin 150-mil soic package information. i 04/04/05 removed 8-contact 6x5 mlp package from document. j 05/09/05 updated and improved ac parameters in table 7.6 and changed t chsh , t clqv and t hlch to reference voltage (2.7v-3.6v / 3.0v- 3.6v) for consistency with other spiflash memory data sheets. k 06/14/05 updated important notice. l 06/28/05 changed nexflash part numbers to winbond part numbers and updated ordering and contact information m 11/28/05 all updated data sheet to comply with winbond standard updated fr and f r values in operating ranges table and ac characteristics table. updated read data (f r ) values in operating range and ac characteristics tables from 33mhz to 25mhz. corrected the pin assignment on table of pin description of page 5.
w25p10, w25p20 and w25p40 publication release date: november 28, 2005 - 35 - revision m preliminary designation the ?preliminary? designation on a winbond data sheet indicates that the product is not fully characterized. the specifications are subject to change and are not g ua ranteed. winbond or an authorized sales representative should be consulted fo r current information before using this product. trademarks winbond and spiflash are trademarks of winbond electronics corporation all other marks are the property of their respective owner. important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgi cal implantation, atomic energy control instruments, airplane or spaceship instrument s, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. the winbond w25p10/20/40 are fully compatible with the previous nexflash nx25p10/20/40 serial flash memories.
w25p10, w25p20 and w25p40 - 36 - headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c.

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